1. Field of the Invention
The present invention relates to a scrambler/descrambler for use in a modulator/demodulator (modem) which is applicable data communication using a telephone network.
2. Description of the Prior Art
In a modem for implementing data communication over a telephone network, a transmit and a receive section have a so-called scrambler and a descrambler, respectively. This is especially true with a modem of the type adopting a particular phase modulation system which is prescribed by CCITT (Comite Consulatif International Telegraphique et Telephonique) Recommendations V.27, V.27bis, V.27ter, etc. A scrambler plays the role of a circuit for randomizing an input signal by a generating polynomial, and preventing codes having relatively short periods ascribable to the nature of a generating polynomial from repeating without being randomized. On the other hand, a descrambler executes a procedure inverse to the randomization which uses a generating polynomial and invalidates the protection against the repetition of codes having relatively short periods as effected by the scrambler, thereby reconstructing the signal.
One of scrambler/descramblers heretofore proposed is implemented by a shift register, a scrambler/descrambler circuit, and a monitor circuit. The monitor circuit is constituted by a counter and a counter control for controlling the counter. While a control output of the counter control is fed to the counter, it is provided with a time delay particular to the propagation path. A clock generator delivers a stepping clock to the counter and is made up of an oscillator and a frequency divider, for example. The scrambler/descrambler circuit has a switch in a data output circuit thereof which is connected to the shift register. The switch is caused into connection with the scrambling side when the apparatus functions as a transmitter or into connection with the descrambling side when the latter functions as a receiver.
The shift register and scrambler/descrambler circuit produces a random code whose period corresponds to 127 bits or decodes such a random code by using a generating polynomial 1+x.sup.-6 +x.sup.-7. The monitor circuit plays the role of a protection circuit for preventing codes having relatively short periods from occurring continuously without being randomized due to the nature of the generating polynomial. Specifically, the monitor circuit inverts the output bits of the scrambler/descrambler circuit when codes whose periods extend to 1-bit, 3-bit and 9-bit periods have occurred continuously for the period of 42 successive bits or when codes whose periods correspond to 2 bits, 4 bits, 6 bits and 12 bits have repeated for the period of 45 successive bits, in association with the ninth and twelfth bit positions of the shift register.
Since the prior art scrambler/descrambler involves bit-by-bit operations as stated above, it cannot be implemented by a processor. In the state of art, despite that a majority of the functions assigned to a modem is executed by a processor, the scrambler/descrambler relies on exclusive hardware in the form of a logical circuit which is independent of the processor. This requires an extra area and extra cost for installing the exclusive hardware. Concerning the processor, the hardware resource, i.e., the time over which the processor can be used and the area which the processor occupies are not efficiently used.